Preparation work before DDR wiring (forwarding)

The first step is to determine the topology structure (only useful for multiple DDR chips)
Firstly, it is necessary to determine the complementary structure of DDR. In one sentence, DDR1/2 adopts a star shaped structure, while DDR3 adopts a daisy chain structure.
The topology only affects the routing of the address line and does not affect the data line. The following is a schematic diagram.

   

The second step is the placement of components

After determining the extension structure of DDR, the components can be placed, and the following principles need to be observed:

Principle one, consider the extension structure, carefully look at the location of the CPU address line, so that the address line is conducive to the corresponding extension structure

Principle 2: The matching resistance on the address line is close to the CPU

Principle three, the matching resistance on the data line is close to the DDR

Principle 4: Place and rotate the DDR chip so that the DDR data line is as short as possible, that is, the data pin of the DDR chip is close to the CPU

Principle 5: If there is a VTT terminal resistor, place it as far as the address line can go. In general, DDR2 does not require VTT termination resistance, which is required by only a few cpus; DDR3 requires a VTT terminal resistor.

Principle six, the decoupling capacitor of the DDR chip is placed near the corresponding pin of the DDR chip

The following is the DDR2 component placement diagram (excluding decoupling capacitors), it can be easily seen that the address line can go to the middle of the two chips and then split to both sides, it is easy to achieve star extension, at the same time, the data line will be very short.

    以下是带有VTT端接电阻的DDR2元器件摆放示意图，在这个例子中，没有串联匹配电阻，VTT端接电阻摆放在了地址线可以到达的最远距离。

    The following is a schematic diagram of DDR3 component placement. Please note that the CPU used here supports dual channel DDR3, so there are four DDR3 chips (8 according to the design). In fact, each two chips form a channel, and the address line is passed along the green line in the diagram, achieving daisy chain expansion. The VTT terminal resistor on the address line is placed as far as the address line can reach. Similarly, the termination resistor of the data line is also placed near the DDR3 chip, and the distance from the data line to the CPU is very short. Meanwhile, it can be seen that the decoupling capacitor is placed very close to the corresponding power pin of DDR3.


    第三步，设置串联匹配电阻的仿真模型
    摆放完元器件，建议设置串联匹配电阻的仿真模型，这样对于后续的布线规则的设置是有好处的。
    点击Analyze->SI/EMI Sim->Model Assignment，如下图。

    Then the Model Assignment interface will be displayed, as shown in the figure below:

Then click on the device that needs to set the model, usually matching resistors in series, to assign or create a suitable simulation of the model.

After allocating the network of the simulation model, use the Show Element command to see the relevant XNET properties, as shown in the following figure

Step 4, set the line width and spacing
1 The line width of DDR wiring is closely related to impedance control, and it is often seen that many peers do impedance control. For pure digital circuits, it is entirely possible to achieve single terminal impedance control for high-speed lines; But for hybrid circuits, including high-speed digital circuits and RF circuits, RF circuits are much more important than digital circuits, and 50 ohm impedance control must be applied to RF signals. At the same time, RF wiring cannot be too thin, otherwise it will cause significant losses. Therefore, in hybrid circuits, I often abandon impedance control of digital circuits. So far, the highest specification DDR in the hybrid circuit products I have designed is DDR2-800, without impedance control, and everything is working normally.
2 The recommended power supply line for DDR is at least 8mil. Allegro can agree to set physical parameters for a certain type of line. I personally like to establish constraints for PWR-10MIL and assign this constraint to all power networks, as shown in the following figure.

    3. 线距部分主要考虑两方面，一是线-线间距，建议采用2W原则，即线间距是2倍线宽，3W很难满足；二是线-Shape间距，同样建议采用2W原则。对于线间距，也可以在Allegro中建立一种约束条件，为所有DDR走线（XNET）分配这样的约束条件，如下图。

   4.Another possible rule that may be needed is the regional rule. The default line width and spacing in Allegro are all 5mil. When the CPU pins are relatively dense, this rule cannot be met. Therefore, it is necessary to set an area rule around the CPU or DDR chip that allows for small spacing and line width, as shown in the following figure.

    Step 5, wiring
There are many things to pay attention to when wiring, and only a few explanations will be provided here.
1. All wiring should be as short as possible
2. The wiring should not have sharp corners
3. Minimize drilling through holes as much as possible
4. Ensure that all wiring has a complete reference plane, either the ground plane or the power plane. For alternating signals, the ground and power planes are equipotential
5. Try to avoid breaking the reference surface through holes, but this is difficult to achieve in practice
6. After wiring the address line and data, be sure to wire all the power pins, ground pins, decoupling capacitor power pins, and ground pins of the DDR chip, otherwise it will be troublesome to wire them with equal lengths later on
The following diagram shows the completed DDR wiring, but it has not yet been wound to an equal length.

Step 6: Set equal length rules

For data lines, DDR1/2 and DDR3 rules are the same: each BYTE is equal in length to its respective DQS, DQM, that is, DQ0:7 and DQS0, DQM. Equal length, DQ8:15 is equal length to DQS1, DQM1, and so on.

DDR2 data cable isometric rule example.

    DDR3数据线等长规则举例。

Pay special attention to the equal length of address lines, as DDR1/2 is very different from DDR.
For DDR1/2, it is necessary to set the distance between each address and the same DDR to maintain an equal length, as shown in the following figure.

For DDR3, the isometric length of the address line often needs to be matched with the through hole. The specific rules are bound to the through hole and the VTT terminal resistor, as shown in the following figure. It can be seen that the distance between the CPU address line and the through-hole is the same length, and the distance between the through-hole and the VTT terminal resistor is the same length.

 

Add that many times, the isometric requirements of the address line are not strict, which I have not tried.In these products designed by me, the isometric rule of 25mil Relative Propagation Delay is set for both the address line and the data line. The details of the isometric rule setting will not be detailed here, if you are interested, you can send an email to Beamsky.

Step seven, around the length

After setting the isometric rules, the last step is also the most laborious step: circling isometric.

At this step, I think there is only one rule to note: try to use 3 times the line width, 45 degrees around the equal length, as shown below.

After completing the isometric winding, it is best to lock the DDR-related network to avoid misoperation.